A 500 MHz 16*16 complex multiplier using self-aligned gate heterostructure FET technology

The authors report a three-stage pipelined 4500-gate 16*16 complex multiplier with a multiply rate of 500 million products per second, producing a complex product which requires four multiplications and two additions every 8 ns at a power dissipation of 4.0 W. The multiplier uses a modified Booth´s algorithm to reduce the number of adders in the multiplier net. The basic building block of the adders and registers is a DCFL NOR gate with a special load structure. The heterostructure active layers were grown by molecular beam epitaxy on 3-in semi-insulating LEC (liquid encapsulated Czochralski) GaAs substrates. The output of bits 1 and 5, operating in the self-test mode, is shown. The circuit was found to perform vector rotations correctly at a clock rate of 560 MHz with a power dissipation of 6.2 W and at 520 MHz with a power dissipation of 4 W. The 520-MHz clock at 4 W corresponds to 96 ps/gate and 0.89 mW/gate because the pipelined stages are limited to 20 gate delays. This performance represents a loaded delay with each gate driving an average fan-out of 2.5 and about 1000 mu m of interconnects at close to minimum spacing.<>