Architecture and implementation of a novel tag computation circuit for broadband wireless access packet scheduling

In this paper we present the hardware architecture and implementation of a tag computation circuit for a credit based Self-Clocked Fair Queuing (SCFQ) scheduler specifically targeted for packet scheduling in Broadband Wireless Access (BWA) as described in the recently released IEEE 802.16 Standards. Our objective is the implementation of a configurable scheduler that is based on the principles of weighted fair queuing combined with a credit based bandwidth reallocation scheme. The implementation provides the hardware platform for a runtime configurable scheduling architecture that is able to reallocate bandwidth on the fly if particular links should suffer packet loss due to unexpected noise or channel quality degradation. The system is implemented using FPGA technology and provides extended programmability to adapt the tag computation to a range of custom scheduling schemes. The hardware architecture is parallel and pipelined enabling an aggregated throughput rate of 180 million tag computations per second. The throughput performance is ideal for BWA nodes, allowing room for relatively complex computations in QoS aware adaptive scheduling. The high-level system breakdown is described and synthesis results for Xilinx FPGA technology are presented.