A 1.5 V DRAM for battery-based applications

Author

Aoki, M. ; Etoh, J. ; Itoh, Kenji ; Kimura, S. ; Kawamoto, Y.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

238

Lastpage

239

Abstract

The authors report low-power, high-signal-to-noise-ratio (SNR) 16 Mbit DRAM (dynamic RAM) techniques which allow 1.5-V battery operation. To reduce power consumption, the data-line voltage swing is the sum of the threshold voltages for nMOS and pMOS transistors in the sense amplifier. A plate-pulse circuit technique, a three-level word pulse, and a 3.4- mu m/sup 2/ data-line shielded STC cell enhance SNR in the memory array. The main features of the DRAM are compared with those of the SNB (storage-node-boosted) technique and a conventional half-V/sub CC/ circuit technique.<>

Keywords

MOS integrated circuits; integrated circuit technology; integrated memory circuits; random-access storage; 1.5 V; 16 Mbit; DRAM; SNB; SNR; battery operation; battery-based applications; conventional half-V/sub CC/ circuit technique; data-line shielded STC cell; data-line voltage swing; dynamic RAM; features; high-signal-to-noise-ratio; low-power; plate-pulse circuit technique; power consumption; storage-node-boosted; three-level word pulse; Batteries; Circuits; DRAM chips; Energy consumption; MOS devices; MOSFETs; Power amplifiers; Pulse amplifiers; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48271

Filename

48271