Field Effect Resistor, a single-device-at-pad solution for ESD protection in deeply scaled SOI technology

In this paper, the FER is shown to be a possible candidate for ESD protection in deeply scaled SOI technology. I_t2 of above 50 mA/μm and capacitance below 0.6 fF/μm are achieved. Despite the FER´s higher resistivity than SOI diode, its major advantage is the dual-directional current shunting capability, such that ESD protection between I/O pads and power buses can be achieved with a single-device solution at the pad instead of several devices. Therefore, this device expands the conventional ESD design space for trading off parameters such as resistivity, I_leak and capacitance. Results from measurements and TCAD simulations further instantiate the advantages of the FERs in current and future SOI technologies. For future technologies such as ultra-thin-film SOI and FinFET, better gate controllability can be achieved to sustain the inversion regions. Thus, the well doping can be increased to lower the resistivity, making the FER more suitable for I/O protection.