• DocumentCode
    3174033
  • Title

    Reliability study in capacitor less 1T-RAM cells on SOI

  • Author

    Aoulaiche, M. ; Collaert, N. ; Simoen, E. ; Mercha, A. ; De Wachter, B. ; Bourdelle, K.K. ; Nguyen, B.Y. ; Boedt, F. ; Delprat, D. ; Jurczak, M. ; Altimime, L.

  • Author_Institution
    IMEC, Heverlee, Belgium
  • fYear
    2010
  • fDate
    11-14 Oct. 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 1016 cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of interface states and carrier trapping at either the source (“0”) or drain side (“1”). Overall reduction of the biases, especially VD, will have a beneficial effect on the endurance behavior.
  • Keywords
    MOSFET; interface states; random-access storage; semiconductor device reliability; silicon-on-insulator; SOI; capacitor less RAM cells; carrier trapping; interface states; reliability study; Charge carrier processes; Degradation; Logic gates; Random access memory; Reliability; Stress; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2010 IEEE International
  • Conference_Location
    San Diego, CA
  • ISSN
    1078-621x
  • Print_ISBN
    978-1-4244-9130-8
  • Electronic_ISBN
    1078-621x
  • Type

    conf

  • DOI
    10.1109/SOI.2010.5641377
  • Filename
    5641377
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3174033