Analysis of the buck converter for scaling the supply voltage of digital circuits

The energy consumption in mobile systems has become a big challenge that limits high performance and autonomy in mobile systems. The dynamic voltage scaling (DVS) is a recent technique that reduces energy consumption varying dynamically the supply voltage of the system accordingly to the clock frequency. The buck topology is a good candidate to supply step variations of the output voltage meeting the DVS requirements. In this paper, it is analyzed which is the fastest output voltage evolution that can provide the Buck topology. The minimum time state transition in the buck converter and its corresponding control law are obtained applying the maximum principle or Pontryagin´s principle. Design criteria for the buck topology are derived from this result. The analysis is extended to a multiphase buck converter. The minimum time control law is validated in a prototype. The measurements are in good agreement with the theoretical results.