Electrical and thermal characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide hybrid substrates

Author

Lotfi, S. ; Vallin, Ö ; Li, L.G. ; Vestling, L. ; Norström, H. ; Olsson, J.

Author_Institution

Angstrom Lab., Uppsala Univ., Uppsala, Sweden

fYear

2010

fDate

11-14 Oct. 2010

Firstpage

1

Lastpage

2

Abstract

150 mm Silicon-on-polycrystalline-Silicon Carbide (poly-SiC) hybrid substrates, without intermediate oxide layers have been realized by hydrophilic wafer bonding of SOI- and poly-SiC wafers. A novel rapid thermal treatment step has been introduced before furnace annealing to avoid bubble formation, cracks and breakage. The final substrates are shown to be stress-free. Electrical and thermal characterization of devices manufactured on the substrate using a MOS process show excellent performance.

Keywords

MIS devices; composite materials; elemental semiconductors; rapid thermal annealing; silicon; silicon compounds; silicon-on-insulator; wafer bonding; MOS process; SOI-SiC wafer; Si-SiC; breakage; bubble formation; cracks; electrical characterization; final substrates; furnace annealing; hydrophilic wafer bonding; novel rapid thermal treatment step; poly-SiC wafer; silicon-on-polycrystalline-silicon carbide hybrid substrates; size 150 nm; stress-free; thermal characterization; Logic gates; Rapid thermal annealing; Resistors; Silicon; Silicon carbide; Substrates; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference (SOI), 2010 IEEE International

Conference_Location

San Diego, CA

ISSN

1078-621x

Print_ISBN

978-1-4244-9130-8

Electronic_ISBN

1078-621x

Type

conf

DOI

10.1109/SOI.2010.5641380

Filename

5641380