• DocumentCode
    3174107
  • Title

    Optimization of RTA process for PVD-TiN gate FinFETs

  • Author

    Liu, Y.X. ; Kamei, T. ; Endo, K. ; O´uchi, S. ; Tsukada, J. ; Yamauchi, H. ; Ishikawa, Y. ; Hayashida, T. ; Matsukawa, T. ; Sakamoto, K. ; Ogura, A. ; Masahara, M.

  • Author_Institution
    Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan
  • fYear
    2010
  • fDate
    11-14 Oct. 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this paper, TR dependence of the device electrical characteristics including Vth and on-state current (Iοn) variabilities as well as the carrier mobility are systematically investigated by fabricating a series of PVD-TiN gate FinFETs at different TR´s.
  • Keywords
    MOSFET; carrier mobility; rapid thermal annealing; titanium compounds; vapour deposition; PVD-TiN gate FinFET; RTA process; carrier mobility; device electrical characteristics; Fabrication; FinFETs; Impurities; Logic gates; Tin; Wet etching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2010 IEEE International
  • Conference_Location
    San Diego, CA
  • ISSN
    1078-621x
  • Print_ISBN
    978-1-4244-9130-8
  • Electronic_ISBN
    1078-621x
  • Type

    conf

  • DOI
    10.1109/SOI.2010.5641382
  • Filename
    5641382
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3174107