Title :
A 16 kb ferroelectric nonvolatile memory with a bit parallel architecture
Author :
Womack, R. ; Tolsch, D.
Author_Institution :
Krysalis Microelectron., Albuquerque, NM, USA
Abstract :
The authors describe an experimental 16-kb nonvolatile memory using two memory cells per bit with one transistor and one ferroelectric capacitor per memory cell. The RAM measures 5 mm*7 mm with 462 mu m/sup 2/ per bit. It is built in a 2- mu m CMOS n-well process and has a chip-enable access time of 200 ns. The authors also demonstrate a bit-parallel architecture in which the common plate of the capacitors runs parallel to the bit lines and connects all bits in a given column. The typical characteristics of the device are given.<>
Keywords :
CMOS integrated circuits; capacitors; ferroelectric devices; integrated memory circuits; random-access storage; 16 kbit; 2 micron; 200 ns; 5 to 7 mm; CMOS; NVRAM; RAM; bit parallel architecture; characteristics; chip-enable access time; ferroelectric capacitor; ferroelectric nonvolatile memory; transistor; two memory cells per bit; Capacitors; Ferroelectric materials; Microelectronics; Nonvolatile memory; Parallel architectures; Polarization; Random access memory; Read-write memory; Testing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48273
