• DocumentCode
    3174401
  • Title

    Experimentally, how does Cu TSV diameter influence its stress state?

  • Author

    Okoro, Chukwudi ; Levine, Lyle E. ; Ruqing Xu ; Obeng, Yaw S.

  • Author_Institution
    Semicond. & Dimensional Metrol. Div., Nat. Inst. of Stand. & Technol. (NIST), Gaithersburg, MD, USA
  • fYear
    2015
  • fDate
    26-29 May 2015
  • Firstpage
    54
  • Lastpage
    58
  • Abstract
    In this work, an experimental study of the influence of Cu through-silicon via (TSV) diameter on stress build up was performed using synchrotron-based X-ray microdiffraction technique. Three Cu TSV diameters were studied; 3 μm, 5 μm and 8 μm, all of which were fabricated in a single chip. Prior to the measurements, the die was annealed at 420 °C (30 min), yielding a fully grown and stable microstructure. The measured mean hydrostatic stresses in the Cu TSV were 185±14 MPa (3 μm Cu TSV diameter), 147±10 MPa (5 μm Cu TSV diameter) and 205±15 MPa (8 μm Cu TSV diameter). As such, no conclusive stress dependence on Cu TSV diameter was determined. This is attributed to stress relaxation mechanisms including plastic deformation, grain boundary sliding, dislocation motion and the formation of cracks/ voids which are otherwise neglected in many reported finite element modeling based studies. Additionally, this study underscores that the stress-strain behavior of Cu TSVs are significantly dependent on their thermal history and microstructural characteristics.
  • Keywords
    X-ray diffraction; copper; finite element analysis; grain boundaries; integrated circuit interconnections; plastic deformation; slip; stress relaxation; three-dimensional integrated circuits; voids (solid); Cu; X-ray microdiffraction technique; copper TSV diameter; crack formation; dislocation motion; finite element model; grain boundary sliding; mean hydrostatic stress; plastic deformation; size 3 mum; size 5 mum; size 8 mum; stress relaxation mechanisms; stress state; temperature 420 C; through-silicon via; time 30 min; void formation; Annealing; Microstructure; Semiconductor device measurement; Strain; Stress; Stress measurement; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
  • Conference_Location
    San Diego, CA
  • Type

    conf

  • DOI
    10.1109/ECTC.2015.7159571
  • Filename
    7159571