Title :
Advanced metallization scheme for 3×50µm via middle TSV and beyond
Author :
Van Huylenbroeck, Stefaan ; Yunlong Li ; Heylen, Nancy ; Croes, Kristof ; Beyer, Gerald ; Beyne, Eric ; Brouri, Mohand ; Gopinath, Sanjay ; Nalla, Praveen ; Thorum, Matthew ; Meshram, Prashant ; Anjos, Daniela M. ; Jengyi Yu
Author_Institution :
Imec vzw, Leuven, Belgium
Abstract :
An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling process. Because of the high conformality of the WN barrier and NiB seed, these layers can be deposited very thinly, reducing the cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall till the bottom of the TSV. This metallization scheme has been successfully processed on 3 m diameter and 50 m deep Via-Middle TSVs, showing void-free copper fill in FIB cross-sections. Good adhesion between liner, barrier and seed was maintained during the processing, including the post plate anneal which is present to reduce the copper pumping. The polishing of the NiB seed and WN barrier has been optimized in order to limit the recess of these layers at the top of the TSV. Electrical results are shown, proving the maturity of this new TSV middle process scheme. Low leakage current in both accumulation and depletion mode is measured. The flat band voltage is low as well, indicating little ionic contamination in the liner oxide. The intrinsic integrity of the liner and the ability of the barrier to prevent Cu diffusion from TSV to silicon has been verified, using the established controlled I-V method. High field acceleration factors are extracted, ensuring good reliability of this advanced and scalable 3×50 TSV middle module.
Keywords :
adhesion; annealing; atomic layer deposition; copper; electrodeposition; focused ion beam technology; integrated circuit metallisation; leakage currents; three-dimensional integrated circuits; tungsten compounds; ALD oxide liner; FIB cross-section; I-V method; NiB; TSV middle process scheme; WN; acceleration factor; accumulation mode; adhesion; advanced metallization scheme; atomic layer deposition; copper ECD filling process; copper diffusion; copper pumping; depletion mode; electrochemical deposition; electroless nickel boride platable seed; flat band voltage; focused ion beam; ionic contamination; leakage current; post plate anneal; thermal ALD tungsten niride barrier; via middle TSV; void-free copper fill; Annealing; Capacitance; Copper; Films; Leakage currents; Metallization; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159573