A 60 ns 3.3 V 16 Mb DRAM

Author

Arimoto, K. ; Fujishima, K. ; Matsuda, Y. ; Oishi, T. ; Tsukude, M. ; Wakamiya, W. ; Satoh, S.-I. ; Yamada, M. ; Yoshihara, T. ; Nakano, T.

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

244

Lastpage

245

Abstract

The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5- mu m, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V/sub cc/=3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; 0.5 micron; 16 Mbit; 3.3 V; 60 ns; DRAM; array architecture; high-speed cache access capability; line mode test; multipurpose register; row-address-strobe access time; small-outline J-leaded package; twin-well CMOS technology; twisted-bit-line; Automatic testing; CMOS technology; Capacitance; Integrated circuit interconnections; Latches; Packaging; Pulse amplifiers; Random access memory; Registers; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48274

Filename

48274