An Approach towards Automation Firmware Modeling for an Exploration and Evaluation of Efficient Parallelization Alternatives

Due to stagnating CPU cycles, future performance gains in automation firmware are unlikely to be achieved without parallelization for multi-core architectures. However, for a sophisticated system comprising millions of lines of code, this process induces significant effort, especially when having to keep real time and safety conditions. As efficiency matters in corporate software development, obtaining maximum speedup by spending no more implementation effort than necessary is intended. Thus, the design of a parallel firmware is recommended to base on the results of a model-based exploration and evaluation of efficient parallelization alternatives. For this purpose, we developed the EEEPA tool chain, that starts with graph-based firmware modeling on basis of dynamic event logs.