Title :
A 55 ns 16 Mb DRAM
Author :
Takeshima, T. ; Takada, M. ; Koike, H. ; Watanabe, H. ; Koshimaru, S. ; Mitake, K. ; Kikuchi, W. ; Tanigawa, T. ; Murotani, T. ; Noda, K. ; Tasaka, K. ; Yamanaka, K. ; Koyama, K.
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm/sup 2/ chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 mu m MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.<>
Keywords :
CMOS integrated circuits; VLSI; automatic testing; integrated circuit testing; integrated memory circuits; random-access storage; 0.6 micron; 16 Mbit; 55 ns; Al; CMOS DRAM; MOS memory cell reliability; access time; automatic test pattern generation procedures; bit-line sense circuits; built-in self-test; chip area; high-speed latched sensing; microprogrammable ROM; peripheral circuits; row-address-strobe access time; sensing speed; Built-in self-test; CMOS technology; Capacitors; Circuit testing; DRAM chips; Random access memory; Silicon compounds; Solid state circuit design; Solid state circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48275
