Title :
A 45 ns 16 Mb DRAM with triple-well structure
Author :
Fujii, S. ; Ogihara, M. ; Shimizu, M. ; Yoshida, M. ; Numata, K. ; Hara, T. ; Watanabe, S. ; Sawada, S. ; Mizuno, T. ; Kumagai, J. ; Yoshikawa, S. ; Kaki, S. ; Saito, Y. ; Aochi, H. ; Hamamoto, T. ; Toita, K.-I.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration.<>
Keywords :
CMOS integrated circuits; VLSI; driver circuits; integrated circuit technology; integrated memory circuits; random-access storage; 16 Mbit; 45 ns; CMOS technology; DRAM; bonding configuration; buried-stacked-capacitor cell; capacitor-plate poly; interdigitated bit-line/shared-sense-amplifier; nibble operation; optimized chip architecture; output waveform; p-channel load word-line bootstrap driver; quarter-pitched arrangement; row-access-strobe access time; scaled-down trench; static column; triple-well structure; well bias; CMOS technology; Circuit noise; Decoding; Delay; Driver circuits; Electrons; Microcomputers; Protection; Random access memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48276
