Title :
Reliability evaluation of an extreme TSV interposer and interconnects for the 20nm technology CoWoS IC package
Author :
Banijamali, Bahareh ; Lee, Tom ; Liu, Henley ; Ramalingam, Suresh ; Barber, Ivor ; Chang, Jonathan ; Kim, Myongseob ; Yip, Laurene
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. This paper presents the development of an extreme TSV interposer technology for three 23 × 14mm die slices that are mounted on a 25 × 45mm silicon interposer with Cu through silicon via. Interposer stitching is achieved either by real lithography stitching of 2 die slices or assembly of 2 adjacent dies (either identical or 2 different photo shots without stitching) together with connections through top dies. The low-k chip is a 20nm chip with total of 375,000 micro-bumps. The silicon interposer is 100um thick, and is mounted on a 55 × 55mm substrate through 30,000 C4 bumps. The substrate has 2892 BGA balls. 3D thermal-mechanical modeling and simulation for the FPGA package with TSV interposer have been performed. The FPGA samples have been subjected to thermal cycling and HTS tests. Effects of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated and measured. Several DOEs have been performed to optimize design and material selection in order to have a reliable 20nm FPGA silicon interposer package that has acceptable warpage/coplanarity, and passes 1000TCB and HTS 1000hrs without any failure or void being seen in low-k, micro bumps and C4 bumps. Furthermore, challenges in manufacturing, handling and reliability of t- is highly rectangular interposer are detailed. Finally, board level test data is presented to show reliability of BGA balls for this 55 × 55mm package.
Keywords :
field programmable gate arrays; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; three-dimensional integrated circuits; size 100 mum; size 14 mm; size 20 nm; size 23 mm; size 25 mm; size 45 mm; size 55 mm; Field programmable gate arrays; Reliability; Silicon; Solid modeling; Stress; Substrates; Temperature measurement;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159604