• DocumentCode
    3175117
  • Title

    A high-speed, long-reach signal design challenge for 2.5-D LSI based on a low-cost silicon interposer and a large-scale SSO analysis

  • Author

    Oikawa, Ryuichi ; Ochiai, Toshihio ; Kida, Tsuyoshi ; Sakata, Kenji ; Kariyazaki, Shuuichi ; Kayashima, Yuji ; Ono, Yoshihiro ; Mori, Ryo ; Nomura, Takao

  • Author_Institution
    Renesas Electron. Corp., Tokyo, Japan
  • fYear
    2015
  • fDate
    26-29 May 2015
  • Firstpage
    293
  • Lastpage
    300
  • Abstract
    A new signal line structure based on a single-sided low-cost silicon interposer is proposed, which extends high-speed signal reaching distance over 16 mm. The proposed signal structure and design scheme are applied to a full-function 2.5-D LSI product that has originally been developed based on a wide-pin pitch organic substrate. Despite a long signal length, the fabricated LSI has successfully worked with a large enough operation margin. This paper also discusses an SSO model reduction technique that enables the analysis of hundreds of parallel signal lines in a practical period. The design method presented in this paper can further extend the range of the low-cost silicon interposer application beyond the usage for wide-I/O or HBM (high bandwidth memory).
  • Keywords
    integrated circuit design; integrated circuit modelling; large scale integration; reduced order systems; SSO model reduction technique; full-function 2.5-D LSI product; high-speed signal reaching distance; parallel signal lines; signal line structure; single-sided low-cost silicon interposer; wide-pin pitch organic substrate; Large scale integration; Mathematical model; Metals; Reduced order systems; Silicon; Substrates; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
  • Conference_Location
    San Diego, CA
  • Type

    conf

  • DOI
    10.1109/ECTC.2015.7159607
  • Filename
    7159607