DocumentCode :
3175350
Title :
Evaluation of a 32-bit microprocessor with built-in concurrent error-detection
Author :
Gaisler, J.
Author_Institution :
Eur. Space Res. & Technol. Centre, Noordwijk, Netherlands
fYear :
1997
fDate :
24-27 June 1997
Firstpage :
42
Lastpage :
46
Abstract :
This paper describes the test results from heavy ion testing of ERC32, a 32-bit processing core with on-chip concurrent error-detection. The parity based error-detection mechanisms succeeded in detecting more than 97.5% of all injected errors, significantly reducing the MTBF for undetected SEU errors. Most errors occurred in registers, but some errors in combinational logic could also be observed. The cross-section for errors in combinational logic is however too small to have an influence on the overall error rate. The conclusion is therefore that parity based error-detection is well suited to detect SEU errors in VLSI devices for space applications.
Keywords :
VLSI; combinational circuits; computer testing; error detection; integrated circuit testing; microprocessor chips; 32-bit microprocessor; ERC32; SEU errors; VLSI devices; built-in concurrent error-detection; combinational logic; heavy ion testing; on-chip concurrent error-detection; parity based error-detection mechanisms; space applications; test results; Circuit testing; Computer errors; Error analysis; Logic devices; Microprocessors; Pipelines; Software testing; Space technology; System testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1997. FTCS-27. Digest of Papers., Twenty-Seventh Annual International Symposium on
Conference_Location :
Seattle, WA, USA
ISSN :
0731-3071
Print_ISBN :
0-8186-7831-3
Type :
conf
DOI :
10.1109/FTCS.1997.614076
Filename :
614076
Link To Document :
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