Title :
Logic Decomposition of Asynchronous Circuits Using STG Unfoldings
Author :
Khomenko, Victor
Author_Institution :
Sch. of Comput. Sci., Newcastle Univ., Newcastle upon Tyne, UK
Abstract :
A technique for logic decomposition of asynchronous circuits which works on STG unfolding prefixes rather than state graphs is proposed. It retains all the advantages of the state space based approach, such as the possibility of multiway acknowledgement, latch utilisation and highly optimised circuits. Moreover, it significantly alleviates the state space explosion, and thus has superior memory consumption and runtime.
Keywords :
Petri nets; asynchronous circuits; circuit CAD; circuit optimisation; flip-flops; logic CAD; STG unfolding prefixes; asynchronous circuits; latch utilisation; logic decomposition; memory consumption; multiway acknowledgement; optimised circuits; runtime; signal transition graph; Boolean functions; Delay; Encoding; Latches; Libraries; Logic gates; Silicon; Logic decomposition; SAT; STG; asynchronous circuits; unfolding;
Conference_Titel :
Asynchronous Circuits and Systems (ASYNC), 2011 17th IEEE International Symposium on
Conference_Location :
Ithaca, NY
Print_ISBN :
978-1-61284-973-7
DOI :
10.1109/ASYNC.2011.10
