Synchronizer Performance in Deep Sub-Micron Technology

We show that the performance characteristics of synchronizer circuits track fabrication feature size reductions in a similar manner to the fan-out-of-four, FO4, inverter delay. We compare a variety of flip-flop circuit designs to a reference cross-coupled inverter circuit and show that flip-flops specifically designed for synchronizer use outperform regular data path flip-flops with the progression of fabrication processes. However, care must be taken to compare circuits in each technology, because additional circuit features have often been added to flip-flop cells with each generation of process. These added features, for example to improve test coverage and facilitate clock selection, frequently degrade synchronizer performance. We present a new synchronizer circuit that performs almost as well as the cross-coupled inverter circuit and has reduced sensitivity to voltage supply variation.