DocumentCode :
3175597
Title :
Extending advanced interconnect technology to finer pitches with conventional mass reflow
Author :
Roa, Fernando
Author_Institution :
Amkor Technol. Inc., Tempe, AZ, USA
fYear :
2015
fDate :
26-29 May 2015
Firstpage :
470
Lastpage :
474
Abstract :
Great efforts have been invested by many equipment and assembly participants to overcome pitch-limited interconnection packaging technology by using advanced solutions like thermo-compression bonding (TB) which enable high placement accuracy and thin-wafer processability. In contrast, the use of conventional convection ovens to achieve high throughput reflow in chip scale packaging has been deemed suitable only for pitches below a certain value, with the exact threshold remaining vague depending on the operator´s process and materials of choice. A key factor in this limitation is the choice of bump metallurgy used, thus solder bumps seems to reach a limit around 150-140-μm pitch vs. copper pillar, whose critical geometry is more definable during plating process, seems to be limited for mass reflow (MR) applications to a pitch around 100 μm. In this paper we examine the role that conventional mass reflow plays in enabling interconnection technology for advanced silicon node devices exhibiting fine bump pitches. While straight implementation of conventional convection oven reflow for fine-pitch applications is more often than not a function of the particular device under assessment, critical go-no-go package attributes were explored and their influence in the final process flow and bill of materials was identified. Their impact in the success of the MR solution is discussed, with relevant examples discussed. A key goal for completing this study is to extend the usability and cost structure of the assets and facilities in mass production today. Final results indicate that is possible to extend mass reflow for devices down to 50 μm in-line pitches or even slightly tighter provided that a few guidelines are followed in terms of bump geometry, substrate design and process tolerance. Yield and cost advantages must surely influence a decision on the part of the end customer in regards to final selection of the interconnection process.
Keywords :
chip scale packaging; copper; fine-pitch technology; integrated circuit bonding; integrated circuit interconnections; reflow soldering; Cu; TB; advanced silicon node devices; bump geometry; bump metallurgy; chip scale packaging; convection oven reflow; copper pillar; final process flow; fine bump pitches; mass production today; mass reflow; pitch-limited interconnection packaging technology; plating process; size 150 mum to 140 mum; solder bumps; thermocompression bonding; thin-wafer processability; Assembly; Copper; Flip-chip devices; Joints; Silicon; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/ECTC.2015.7159633
Filename :
7159633
Link To Document :
بازگشت