2B1Q transceiver for the ISDN subscriber loop

Author

Koch, R. ; Niggebaum, R. ; Vogel, D.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

260

Lastpage

261

Abstract

A transceiver chip set for the ISDN (integrated services digital network) digital subscriber loop using quaternary code (2B1Q) is described which features full-duplex transmission with 144-kb/s net bit rate using the hybrid-balancing principle together with digital adaptive echo cancellation. The two-chip set provides the physical interface between the network termination and the digital exchange according to the T1D1 layer 1 specification for the ISDN basic access interface. A serial multiplexed standard interface allows connection to circuits supporting the layer 2 protocol control at the exchange side of the standard S-bus at the NT. Chip characteristics are listed, and block diagrams are presented.<>

Keywords

ISDN; echo suppression; protocols; standards; subscriber loops; transceivers; 144 kbit/s; 2B1Q transceiver; ISDN subscriber loop; T1D1 layer 1 specification; chip set; digital adaptive echo cancellation; full-duplex transmission; hybrid-balancing principle; layer 2 protocol control; network termination; quaternary code; serial multiplexed standard interface; standard S-bus; Circuits; Clocks; Delta-sigma modulation; Echo cancellers; Error correction; Finite impulse response filter; ISDN; Subscriber loops; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48281

Filename

48281