Limitations of the two-frequency capacitance measurement technique applied to ultra-thin SiO2 gate oxides

An improved two-frequency C-V extraction guideline for ultra-thin gate structures is proposed. The measured dissipation should be less than 1.1 at least at one of the two measurement frequencies, in order to reduce the gate oxide thickness measurement error below 4%. We show that the proposed guideline sets certain limitations on the device area, which must be reduced as the gate oxide shrinks, in order to keep the dissipation below 1.1, while not increasing the device impedance above the measurement limit of the LCR meter. We have also demonstrated that an additional parasitic inductance effect must be included in the equivalent circuit model if the measurement frequency is above 1 MHz