Fault-tolerance of spaceborne semiconductor mass memories

Author

Fichna, T. ; Gartner, M. ; Gliem, F. ; Rombeck, F.

Author_Institution

Inst. fur Datenverabeitungsanlagen, Tech. Univ. Braunschweig, Germany

fYear

1998

fDate

23-25 June 1998

Firstpage

408

Lastpage

413

Abstract

The architecture of spaceborne Semiconductor Mass Memories is mainly determined by the requirements on reliability and data integrity. The highly granular structure of the memory kernel supports the implementation of hierarchical redundancy structures. Error correcting codes are in use to cope with particle induced bit errors. For protection of 4-bit wide devices an extended Reed-Solomon (78,64) SSC DSD code is appropriate and well suited to a low expenditure H/W implementation of coding and checking.

Keywords

Reed-Solomon codes; aerospace computing; error correction codes; fault tolerant computing; memory architecture; redundancy; semiconductor storage; space vehicle electronics; checking; coding; data integrity; error correcting codes; hierarchical redundancy structures; low expenditure H/W implementation; memory kernel; particle induced bit errors; reliability; spaceborne semiconductor mass memories; Degradation; Error correction codes; Fault tolerance; Mars; Memory architecture; Protection; Redundancy; Reed-Solomon codes; Single event upset; Space missions;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Computing, 1998. Digest of Papers. Twenty-Eighth Annual International Symposium on

Conference_Location

Munich, Germany

ISSN

0731-3071

Print_ISBN

0-8186-8470-4

Type

conf

DOI

10.1109/FTCS.1998.689492

Filename

689492