Title :
On fault-tolerant PLA design
Author :
Lala, P.K. ; Tao, D.L.
Author_Institution :
Dept. of Electr. Eng., North Carolina Agric. & Technol. State Univ., Greensboro, NC, USA
Abstract :
Summary form only given. A technique for making embedded programmable logic arrays (PLAs) tolerant of cross-point faults is presented. A technique for repairing PLAs, used as components in VLSI chips. is described. The technique proposed for embedded PLAs can achieve cross-point fault tolerance by incorporating a single spare product line and a few programmable switches. A PLA with three inputs, five product terms, and two outputs is outlined. The bit lines and the sum lines are connected to the spare product line via special switches. Such switches consist of a transistor and a normally ON link. An additional column of normally ON links is placed between the load transistor and the product lines. If a growth or a shrinkage fault is detected in a product line, the normally ON link associated with the product line is changed to OFF, thus disconnecting the product line from its load transistor. The spare product line is then programmed to replace the faulty one by appropriately changing the status of the ON links in the switches to OFF
Keywords :
fault tolerant computing; logic arrays; logic design; cross-point fault tolerance; cross-point faults; embedded programmable logic arrays; fault-tolerant; Circuit faults; Electrical fault detection; Fault detection; Fault tolerance; Logic arrays; Logic devices; Notice of Violation; Programmable logic arrays; Switches; Transistors;
Conference_Titel :
Southeastcon '90. Proceedings., IEEE
Conference_Location :
New Orleans, LA
DOI :
10.1109/SECON.1990.117959
