Title :
A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design
Author :
Takaura, N. ; Nagai, R. ; Asakura, H. ; Yamada, S. ; Kimura, S.
Author_Institution :
Central Res. Lab., Hitachi Ltd, Tokyo, Japan
Abstract :
We developed a method for analyzing boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. N + gate PMOSFETs, which are immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs. We found that Vth fluctuation in P+ gate PMOSFETs is dominated by boron penetration and that it is possible to select high-performance Gbit DRAM fabrication processes that are robust against Vth fluctuation
Keywords :
CMOS memory circuits; DRAM chips; MOSFET; boron; doping profiles; fluctuations; integrated circuit testing; DRAM design; DRAM fabrication processes; N+ gate PMOSFETs; P+ dual-gate PMOSFETs; Si:B; boron penetration; boron penetration immunity; dual-gate PMOSFETs; gate depletion; gate depletion immunity; threshold voltage fluctuation; threshold voltage shifts; Boron; Fabrication; Fluctuations; Laboratories; MOSFETs; Performance analysis; Photonic band gap; Random access memory; Silicon; Threshold voltage;
Conference_Titel :
Microelectronic Test Structures, 2001. ICMTS 2001. Proceedings of the 2001 International Conference on
Conference_Location :
Kobe
Print_ISBN :
0-7803-6511-9
DOI :
10.1109/ICMTS.2001.928657
