Title :
Test chip for electrical linewidth of copper-interconnect features and related parameters
Author :
Cresswell, M.W. ; Arora, N. ; Allen, R.A. ; Murabito, C.E. ; Richter, C.A. ; Gupta, A. ; Linholm, L.W. ; Pachura, D. ; Bendix, P.
Author_Institution :
Semicond. Electron. Div., Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
Abstract :
This paper reports a new electrical test structure for measuring the barrier-layer thickness and total physical linewidth of copper-cored interconnect features. The test structure has four critical dimension (CD) reference segments of different drawn linewidths. A new linewidth-extraction algorithm has been developed and extensively tested with ⟨V/I⟩ and sheet-resistance measurement emulations. It has also been applied to measurements extracted from scaled-up physical structures. A second test structure for measuring conducting feature and interlayer-dielectric (ILD) thickness by use of the charge-based capacitance method (CBCM) is located on the test chip. Test-chips featuring both of these structures have been patterned in aluminum using a standard 0.18 μm CMOS process and preliminary results are reported here
Keywords :
CMOS integrated circuits; capacitance; copper; dielectric thin films; electric resistance; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit testing; size measurement; 0.18 micron; Al; CD reference segments; CMOS process; Cu; ILD thickness; aluminum patterning; averaged V/I measurement emulations; barrier-layer thickness; charge-based capacitance method; conducting feature thickness; copper-cored interconnect features; copper-interconnect features; copper-interconnect parameters; critical dimension reference segments; drawn linewidths; electrical linewidth; electrical test structure; interlayer-dielectric thickness; linewidth-extraction algorithm; scaled-up physical structures; sheet-resistance measurement emulations; test chip; test structure; total physical linewidth; Aluminum; CMOS process; Capacitance measurement; Current measurement; Electric variables measurement; Emulation; LAN interconnection; Semiconductor device measurement; Testing; Thickness measurement;
Conference_Titel :
Microelectronic Test Structures, 2001. ICMTS 2001. Proceedings of the 2001 International Conference on
Conference_Location :
Kobe
Print_ISBN :
0-7803-6511-9
DOI :
10.1109/ICMTS.2001.928659
