Design and implementation of a parallel processing Viterbi decoder using FPGA

Convolution encoder and Viterbi decoder are widely used in many communication systems due to the excellent error control performance. This paper deals with the design and implementation of convolution encoder and Viterbi decoder using Field Programmable Gate Array. By analysis the algorithm of Viterbi decoder, the paper explores a practical method to design a parallel processing Viterbi decoder. It means trace back and decoder can simultaneously work in order to improve the processing speed. The experimental results show that this method is feasible, and some of the implementation issues related to the Viterbi decoder, such as branch metric unit, add compare select, memory unit and trace back have also been discussed.