Title :
Evaluation of high-performance SOI complementary BiCMOS devices by using test structures
Author :
Tamaki, Yoichi ; Iwasaki, Takayuki ; Tsuji, Kousuke ; Chida, Yoshinobu ; Tomatsuri, Toshiyuki ; Yoshida, Eiichi ; Kumazawa, Jun ; Kamada, Chiyoshi
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
We used new test structures to evaluate the performance of complementary bipolar transistors fabricated on a SOI substrate by a new 0.35 μm complementary BiCMOS process. The fabricated NPN transistors have a cut-off frequency (fT) of 10.5 GHz at a C-E breakdown voltage of 19.5 V and the PNP transistors have fT of 6.0 GHz at 17.8 V. The test structure measurement showed that the high performance is due to the new isolation structure of the BiCMOS transistor and its layout
Keywords :
BiCMOS integrated circuits; bipolar transistors; capacitance; integrated circuit layout; integrated circuit testing; isolation technology; silicon-on-insulator; 0.35 micron; 10.5 GHz; 17.8 V; 19.5 V; 6 GHz; BiCMOS transistor; BiCMOS transistor layout; C-E breakdown voltage; NPN transistors; PNP transistors; SOI complementary BiCMOS devices; SOI substrate; Si-SiO2; complementary BiCMOS process; complementary bipolar transistors; cut-off frequency; isolation structure; performance evaluation; test structure measurement; test structures; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Cutoff frequency; Frequency measurement; Laboratories; Metal-insulator structures; Substrates; Testing; Very large scale integration;
Conference_Titel :
Microelectronic Test Structures, 2001. ICMTS 2001. Proceedings of the 2001 International Conference on
Conference_Location :
Kobe
Print_ISBN :
0-7803-6511-9
DOI :
10.1109/ICMTS.2001.928670
