A fixed width scheme for reconfigurable recursive multipliers

This paper presents an unsigned truncated recursive multiplier architecture based on the variable correction method. The proposed design can be partitioned to perform as one N-bit fixed width multiplier or as two N/2-bit full precision multipliers. Design targets single level recursive multiplier architecture. Exhaustive analysis was carried out to calculate the maximum error bound in case of truncated multiplier. Experimental results show a maximum negative error bound of -0.6 and mean of 0.026 with hardware savings of 25% in case of fixed width multiplier.