Title :
An economic lab design for hands-on education in microelectronics processing
Author_Institution :
Dept. of Mater. Eng., California Polytech. State Univ., San Luis Obispo, CA, USA
Abstract :
Although microelectronics processing is a field that demands more and more of the nation´s engineers, few institutions are set up to provide undergraduate students with a hands-on education. Laboratories that are equipped with state-of-the-art technology are often prohibitively expensive for smaller institutions, costing $500/square foot for facilities alone. The laboratory design that is presented in this paper was implemented for roughly $32/square foot. Its design is based on the concept of a room within a room. It allows the fabrication of a 4-mask level PMOS integrated circuit using technology that educates students on the concepts with a minimum of safety hazards
Keywords :
MOS integrated circuits; electronic engineering education; laboratories; student experiments; 4-mask level PMOS integrated circuit; economic laboratory design; hands-on education; microelectronics processing; safety hazards; state-of-the-art technology; students; Buildings; Costing; Filters; Fires; Foot; Laboratories; Microelectronics; Steel; Ventilation; Welding;
Conference_Titel :
Frontiers in Education Conference, 1997. 27th Annual Conference. Teaching and Learning in an Era of Change. Proceedings.
Conference_Location :
Pittsburgh, PA
Print_ISBN :
0-7803-4086-8
DOI :
10.1109/FIE.1997.635962