Signal integrity analysis and optimization for 3D ICs

This paper studies the TSV-to-TSV coupling issues in 3D ICs and introduces a methodology for performing signal integrity (SI) analysis considering TSV-to-TSV coupling for 3D ICs. 3D SI analysis results show that TSV coupling has big impact on the SI in 3D ICs. A TSV-KOZ sizing methodology and a force-directed placement-refinement approach are proposed to alleviate the 3D SI problem. Experimental results show that using different larger KOZ sizes can achieve a 22%-55% total coupling-noise reduction and a 12%-39% critical path delay reduction. By using placement refinement approach, the total coupling-noise is reduced by 32% and the critical path delay is reduced by 10% while maintaining the same chip area. Therefore these two approaches are both effective in alleviating the TSV-caused SI problems in 3D ICs.