A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers

Author

Wieckowski, Michael ; Chen, Gregory K. ; Kim, Daeyeon ; Blaauw, David ; Sylvester, Dennis

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA

fYear

2011

fDate

14-16 March 2011

Firstpage

1

Lastpage

4

Abstract

A 128 kb portless SRAM is presented with 1024 rows per hierarchical bitline and CMOS thyristor-based local sense amplifiers. Each portless cell is 0.317 μm² in 45 nm CMOS and consumes 50.8 fJ of energy per access at a 17.86 ns cycle time. A 65% read SNM improvement and a 33% leakage power reduction is achieved over a conventional 6T design. The thyristor-based sense amplifier occupies 2.4 μm² and provides variation tolerant sensing within the hierarchical column pitch.

Keywords

CMOS memory circuits; SRAM chips; amplifiers; thyristor circuits; CMOS thyristor-based local sense amplifier; SNM improvement; hierarchical bitlines; hierarchical column pitch; high density portless SRAM; leakage power reduction; memory size 128 KByte; size 45 nm; Arrays; Metallization; Noise; Organizations; Random access memory; Standards organizations; SRAM; low-power; memory; noise-margin; stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ISQED), 2011 12th International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1948-3287

Print_ISBN

978-1-61284-913-3

Type

conf

DOI

10.1109/ISQED.2011.5770708

Filename

5770708