3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement

While 3D integration using through-silicon vias (TSVs) offers an opportunity to realize higher-performance subsystems than conventional SOC, the potential compound yield loss leads to worse cost control, which becomes a major hindrance to its mass production. Among many outstanding issues to be resolved, one is induced from insufficient bonding strength and quality, resulting in unreliable or even failing die stacking. In this paper, we present a bond pad doubling approach to enhance the TSV-based 3D IC manufacturing yield and reliability. It aims to be easily incorporated into the current physical design flow by leveraging mature 2D layout tools. First, to maximize the pattern density and meet the lower limit, dummy bond pads are inserted into the whitespace between dies. Next, for bond pad doubling, a greedy assignment is applied to select from the dummy at the neighborhood by incremental routing on the front side of the lower die, which connects the singles to form pairs. Finally, the connections are copied to the corresponding back metal of the upper die. Empirical results demonstrate that the proposed approach can promisingly achieve an initial success rate as high as 80% with the nearest neighbors. To further enhance the quality of results, bond padding technique is also applied to the work. The final success rate is up to 95%. The bonding yield and strength can be effectively improved.