Novel and efficient min cut based voltage assignment in gate level

In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried to be shortened with the minimized power increment until the timing constraints are satisfied. Experimental results show that given dual-vdd, our method beats traditional methods both in power saving and runtime, especially runtime.