A design time simulator for computer architects

Processor design and implementation is a complex and resource intensive enterprise. Ideally, designers should be able to quantify the design time implications of their architectural proposals, in order to make more educated decisions and design trade offs. To address the lack of quantitative methodologies to estimate processor design time, this paper introduces a new class of event-driven simulation: μDSim. Our proposed simulation infrastructure models the interaction between engineers during the development and verification cycles. To validate μDSim, we compare estimated design times against data gathered during the development and verification of three different academic processors and three industrial multiprocessor systems. As an example application for the architectural community, we estimate the design time for a previously published architectural proposal.