Title :
Feature resolution capability for stencil printed TLPS paste interconnect structures
Author :
Shearer, Catherine ; Holcomb, Ken ; Haley, Jim
Author_Institution :
Ormet Circuits, Inc., USA
Abstract :
Electronics packaging is an industry in flux, with packaging levels undergoing an unprecedented level of convergence. A wide variety of new interconnect strategies are under investigation. TLPS pastes offer a unique combination of versatility of deposition, maintenance of deposition footprint during reflow, lack of remelt, platability, and solderability after processing that can produce a wide variety of interconnect structures. Features formed from TLPS pastes may be deposited by a number of techniques including stencil printing and dispensing. Stencil printing offers the opportunity to create multiple features in a single operation for high throughput and versatility. The study presented in this paper explores the capability of TLPS pastes in conjunction with state-of-the-art stencil and stencil printing technology. The TLPS pastes investigated have been optimized to provide high retention of printed feature shape through reflow processing and offer direct solderability for compatibility with a wide variety of interconnect schemes. First, the area ratio limitations for deposition of TLPS pastes in state-of-the-art stencils with nano release coatings will be explored as a function of particle size distribution and rheology variations. Next the retention of deposition shape and footprint on copper and ENIG surfaces will be considered through nitrogen reflow. Finally, the ability of the processed deposits to subsequently be soldered will be characterized. The purpose of the study is to provide design rules for the use of TLPS interconnects in a wide variety of interconnection structures where stand-off, pitch, and multiple reflow environments present interconnect challenges.
Keywords :
convergence; copper; electronics packaging; interconnections; liquid phase deposition; particle size; reflow soldering; rheology; solders; ENIG surface; convergence; copper; deposition footprint; deposition shape retention; electronics packaging; feature resolution capability; interconnect strategy; nano release coating; nitrogen reflow; packaging level; particle size distribution; platability; reflow processing; rheology variation; solderability; stencil dispensing; stencil printed TLPS paste interconnect structure; stencil printing technology; transient liquid phase sintering; Assembly; Copper; Integrated circuit interconnections; Printing; Shape; Surface treatment;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159752