DocumentCode :
3178028
Title :
Efficient directed test generation for validation of multicore architectures
Author :
Qin, Xiaoke ; Mishra, Prabhat
Author_Institution :
Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL, USA
fYear :
2011
fDate :
14-16 March 2011
Firstpage :
1
Lastpage :
8
Abstract :
Functional verification of multicore architectures is widely acknowledged as a major challenge. Directed tests are promising since a significantly smaller number of directed tests can achieve the same coverage goal compared to constrained-random tests. SAT-based bounded model checking is effective for automated generation of directed tests (counterexamples). While existing approaches focus on clause forwarding between different bounds to reduce the test generation time, this paper proposes a novel technique that exploits the structural similarity within the same bound as well as between different bounds. Our proposed technique enables the reuse of the knowledge learned from one core to the remaining cores in multicore architectures. The experimental results demonstrate that our approach can significantly (2-10 times) reduce overall test generation time compared to existing approaches.
Keywords :
automatic test pattern generation; formal verification; integrated circuit testing; microprocessor chips; multiprocessing systems; SAT based bounded model checking; automated test generation; directed test generation; functional verification; multicore architecture validation; Acceleration; Encoding; Indexes; Life estimation; Multicore processing; Safety;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-61284-913-3
Type :
conf
DOI :
10.1109/ISQED.2011.5770737
Filename :
5770737
Link To Document :
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