Global transaction ordering in Network-on-Chips for post-silicon validation

Author

Gharehbaghi, Amir Masoud ; Fujita, Masahiro

Author_Institution

VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan

fYear

2011

fDate

14-16 March 2011

Firstpage

1

Lastpage

6

Abstract

This paper presents a method to extract global order of transactions from local partial orders in NoC tiles. The ordering method is based on our set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. We have improved the extracted global order by considering the information from the neighboring tiles. We have studied the effect of our method on global ordering of transactions in mesh and torus topologies with different sizes from 5*5 to 9*9. We have shown that by considering neighboring information, global ordering improves 1.9 to 5.1 times depending on topology and network size.

Keywords

integrated circuit design; network topology; network-on-chip; NoC tile; global transaction ordering; happened-before rule set; mesh topology; network-on-chip; post-silicon validation; torus topology; Complexity theory; IP networks; Network topology; Synchronization; System-on-a-chip; Tiles; Topology; network-on-a-chip (NoC); post-silicon validation; system-on-a-chip (SoC); transaction ordering;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ISQED), 2011 12th International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1948-3287

Print_ISBN

978-1-61284-913-3

Type

conf

DOI

10.1109/ISQED.2011.5770738

Filename

5770738