A layer prediction method for minimum cost three dimensional integrated circuits

We propose a layer prediction method. It may be applied to automatically partition a gate-level netlist into a minimum cost 3D IC. The number of layers of the lowest cost 3D IC design is noted as Min_Cost_Layer of the design. We develop a multilevel multilayer partitioning program. It partitions a gate level netlist into a K-layer 3D IC structure. Its objective is to minimize the total number of TSVs under an area constraint. The program is applied to benchmark circuits to study the relation between the cost of 3D ICs and the number of partition layer K. The relation shows two classes of curves. One class shows “smiling” curves and the other shows “upward” curves. Our study shows the Min_Cost_Layer of a circuit depends on the ratio of total TSV area to the die area. We also find the upper bound of the Min_Cost_Layer. Therefore, we propose two methods: “Less_TSV” and “More_TSV” prediction methods. According to the processing technology and connectivity of a circuit, we select the appropriate method. The experimental results show that combining the Min_Cost_Layer prediction methods and the partitioning program, we can get the minimum cost 3D IC of a circuit effectively. For the 9 test circuits, on average, the cost of 3D implementations may save 13.74% compared with 2D implementations.