Shared cryptography accelerator for multicores to maximize resource utilization

This paper proposes a single crypto unit sharing multicores to accelerate the execution of cryptography applications and to make efficient use of the on-chip resources. The shared accelerator is based on the AES algorithm, where parallel AES pipelines are used for high throughput encrypting/decrypting data. For simplicity, the host processor contains four cores; each core consists of a simple five-stage, single-issue pipeline. Each core fetches an instruction from its instruction cache and sends it in-order to the decode stage. Crypto instructions are pushed into the crypto instruction queue (CIQ) during the decode stage, however, scalar instructions complete the remaining cycle of execution on the scalar pipeline stages. There is a CIQ in the shared crypto unit for each core, where crypto instructions are read from CIQs in round-robin fashion for execution on the parallel AES pipelines. On Xilinx Virtex V FPGA, our results show a maximum throughput of 45 Giga bits per second at 400 MHz.