Review of wafer dicing techniques for via-middle process 3DI/TSV ultrathin silicon device wafers

Dicing of ultrathin (e.g. <; 75um thick) “via-middle” 3DI/TSV semiconductor wafers proves to be challenging because the process flow requires the dicing step to occur after wafer thinning and back side processing. This eliminates the possibility of using any type of “dice-before-grind” techniques. In addition, the presence of back side alignment marks, TSVs, or other features in the dicing street can add challenges for the dicing process. In this presentation, we will review different dicing processes used for 3DI/TSV via-middle products. Examples showing the optimization process for a 3DI/TSV memory device wafer product are provided.