Title :
Automatic post-layout flow validation tool for Deep Sub-micron process design kits
Author :
Sun, Pinping ; Zemke, Cole ; Woods, Wayne H. ; Perez, Nick ; Wang, Hailing ; Mina, Essam ; Dewitt, Barbara
Author_Institution :
IBM, Hopewell Junction, NY, USA
Abstract :
This paper presents a novel automated post-layout flow validation tool to intensively test the MOSFETs and passive components in 32nm, 28nm and 22nm Process Design Kits (PDK). Benchmark circuits, such as, ring oscillator, logic circuits and passive delay circuits, are automatically generated, LVS (layout versus schematic) checked, extracted and simulated in multiple Model/LVS/Parasitic extraction(PEX) test flows. By using the proposed tool, the delay differences (deltas) between the different test flows are cross verified to assure the functionality and accuracy of Model, LVS and PEX before PDK release. Combined with field solver validation, the automated post-layout flow validation significantly improves the quality and reduces the development time of Deep Submicron (DSM) PDKs.
Keywords :
MOSFET; circuit CAD; circuit simulation; integrated circuit design; process design; semiconductor device testing; DSM; LVS; MOSFET; PDK; PEX; automatic post-layout flow validation tool; benchmark circuit; deep submicron process design kit; layout versus schematic; logic circuits; model-LVS-parasitic extraction; passive delay circuit; ring oscillator; size 22 nm; size 28 nm; size 32 nm; Accuracy; Benchmark testing; Capacitance; Delay; Integrated circuit modeling; Layout; Resistance; Deep Submicron (DSM); Process Design Kits (PDK); benchmark circuit; delay differences (deltas); parasitic extraction (PEX); tool validation;
Conference_Titel :
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-61284-913-3
DOI :
10.1109/ISQED.2011.5770769
