Opto-electronic phase-locked loop using four-wave mixing in a semiconductor optical amplifier

Clock recovery is an important function of any digital communications system, critical for receiving and possibly regenerating the signal. A heterodyne PLL in which FWM in a SOA replaces the high-frequency mixer, has been proposed for purely RZ signals and demonstrated at 16×6.3 Gbps and reproduced by us at l0 Gbps with both RZ and NRZ signals. A drawback of this scheme is that the generated clock is in electrical form, whereas an all-optical regenerator, by definition, requires an optical clock. Therefore we also demonstrate an alternate scheme, more akin to a conventional single-stage PLL -still based on FWM in a SOA-that does produce a clock in optical form. The lock bandwidth was 6 kHz and the RMS jitter is estimated at 3.8 ps and the bit error ratio measurements show little or no penalty.