Silicon Interposer warpage estimation model for 2.5D IC packaging utilizing passivation film composition and stress tuning

Latest portable or consumer electronic devices have driven packaging technology and industry towards the direction of 3D IC for vertical interconnection between homogenous or heterogeneous chips integration based on diverse applications. Since 3D IC packaging certainly possesses several obstacles and challenges during research & development, foundries and Outsourced Semiconductor Assembly and Test (OSAT) have focused on a much simplified approach known as 2.5D IC packaging, which utilizes technology called Through Silicon Via (TSV) and well-designed Re-Distribution Layer (RDL) to achieve electrical interconnection. 2.5D IC packaging not only provides us with the advantages of smaller package dimension and greater electrical performance, but considerably reduces numerous challenges which 3D IC packaging may incline to generate. SPIL has participated in the vast domain of 3D IC packaging since early 2012 by establishing our in-house 2.5D IC packaging capability. We have developed corresponding technologies for traditional Chip-on-Chip (CoC) platform and moved on to latest Chip-on-Wafer (CoW) or Chip-to-Wafer (CtW) platform combining Through Silicon Interposer (TSI) with Backside Via Reveal (BVR) and RDL process. Last year, we proposed several actions for the fabrication process challenges which we have encountered during 2.5D IC packaging development, including warpage alleviation for interposer, passivation film thickness tuning, and passivation film interface delamination prevention [1]. In the latter half of 2014, extensive studies and works have been focused on warpage alleviation for interposer, which consisted of further investigation about passivation film composition, material stress behavior, film thickness, film uniformity, and so forth. It was expected that a much robust correlation or model can be derived and acquired to help us estimate warpage performance at different process stages, assisting us in determining the influences of thermal process and- material stress distribution. In this paper, we have expanded the estimation model from one-layer passivation film tuning to dual-layer passivation film tuning using composite passivation materials including Silicon Dioxide (SiO₂), Silicon Nitride (SiN_x), and various types of stress-altered SiN_x with different stress behavior. The mutual relationship and effects of passivation film stress behavior, film thickness, dual-layer configuration, and corresponding thermal influences were both investigated and addressed. This estimation model can be further expanded and fitted into a multi-level passivation film structure if required, and it was proven to be effective for predicting diverse interposer designs and structures from design houses much efficiently. It was anticipated that the estimation model with robust theoretical basis and explicit analysis can be utilized for contributing to solving 2.5D IC packaging warpage issues and lowering the gap for moving on to 3D IC packaging development in swifter advancement.