Digitally programmable SRAM timing for nano-scale technologies

Embedded memory is a critical component of modern SOCs. In highly scaled CMOS, process variability and device aging degradation cause a significant increase in the soft failure rate of embedded SRAMs. As process technology continues to scale, these issues become more pronounced, especially when the device is operating at its minimum operating voltage, V_{DD MIN}. This failure rate can even exceed the maximum repair capacity of the SRAM resulting in yield loss. Guard bands in signal timing can be introduced to mitigate this loss, however it comes at the cost of excessive power dissipation and read access time. Digitally programmable timing allows for a code based, post-fabrication optimization approach to reduce the soft failure rate, and in turn maximize yield, while minimizing excessive power dissipation and read access time. Additionally, the digital code can be re-calibrated over time to compensate for continued device parameter drift due to aging degradation.