Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis

The mismatch of current sources is caused by the circuit error and the process variation. Introducing the channel length modulation λ to the Pelgrom model for variation analysis, we describe a new ΔI/I model of current sources. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90nm process technology, where we can collect the characteristics variation for MOSFETs of various layout structures. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Compared to the variation values by removing the circuit errors ϵ from the measured DNLs, we show that our ΔI/I model with Δλ is more accurate than the original Pelgrom model. Furthermore, we reveal the layout dependency in our model for higher accuracy.