Thermal performance of flip chip using finite element method

Author

Hassan, A.Y. ; Seetharamu, K.N.

fYear

1998

fDate

27-30 May 1998

Firstpage

22

Lastpage

26

Abstract

This study deals with the use of finite element methods to determine the thermal performance and limits of flip chip packaging. The simulations show good agreement with available experimental data. The thermal limit study of the above package (based on the constraint of maximum junction temperature) shows that the limit of power dissipation is 1.7 W for the basic package under free convection and 1.9 W for forced convection. For the enhanced package (with heat sink), the limits are found to be 6.7 and 13.7 W for the cases of free and forced convection, respectively. This method offers greater ease of economical assessment of the thermal performance and limits of a variety of packages in comparison with other methods like CFD

Keywords

circuit simulation; finite element analysis; flip-chip devices; forced convection; integrated circuit packaging; integrated circuit testing; natural convection; thermal analysis; thermal management (packaging); 1.7 W; 1.9 W; 13.7 W; 6.7 W; CFD; enhanced package; finite element method; flip chip; flip chip packaging; forced convection; free convection; heat sink; maximum junction temperature constraint; packages; power dissipation; simulations; thermal limits; thermal performance; Computational fluid dynamics; Electronic packaging thermal management; Electronics packaging; Finite difference methods; Finite element methods; Flip chip; Heat sinks; Pins; Thermal conductivity; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal and Thermomechanical Phenomena in Electronic Systems, 1998. ITHERM '98. The Sixth Intersociety Conference on

Conference_Location

Seattle, WA

ISSN

1089-9870

Print_ISBN

0-7803-4475-8

Type

conf

DOI

10.1109/ITHERM.1998.689515

Filename

689515