Title :
Achieving warpage-free packaging: A capped-die flip chip package design
Author :
Yuci Shen ; Leilei Zhang ; Xuejun Fan
Author_Institution :
Lamar Univ., Beaumont, TX, USA
Abstract :
Coefficient of thermal expansion (CTE) mismatch between chip and substrate is the root cause for reliability issues in flip chip packages, such as excessive warpage, low-k dielectric layer cracking, solder mask cracking, and bump cracking. The first and foremost thing in designing a flip chip package is to control excessive warpage to meet the warpage specification. In this paper, a capped-die flip chip package is proposed to control the warpage as well as to reduce the stress. In the capped-die flip chip package, a metal cap tightly covers and bonds with the die through an adhesive material. As a result, the capped-die has a higher effective CTE. By adjusting the thickness of metal cap, the effective CTE of the capped-die can matches with the CTE of substrate, theoretically achieving zero-warpage or warpage-free. To verify the capped-die concept for zero-warpage control, a 45mm×45mm size of capped-die flip chip package is designed and manufactured based on the guidance from finite element modeling, where a copper die-cap with 0.4mm thickness is selected. Then, Shadow Moiré test is performed to measure the warpage as function of temperature from 25°C to 260°C. Experimental data show that in the temperature range, the warpage curve of the capped-die package is almost flat and close to zero, verifying the capped-die concept.
Keywords :
adhesives; finite element analysis; flip-chip devices; integrated circuit reliability; thermal expansion; CTE; Shadow Moiré; adhesive material; bump cracking; capped-die flip-chip package design; coefficient thermal expansion mismatch; excessive warpage control; finite element modeling; low-k cracking; metal cap; reliability; solder mask cracking; stress reduction; temperature 25 degC to 260 degC; warpage-free packaging; Curing; Finite element analysis; Flip-chip devices; Metals; Reliability; Stress; Substrates;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159803