A novel approach for CMOS parallel counter design

This paper presents novel low-power high-performance CMOS parallel counter circuits based on recently proposed shift switch logic utilizing state signals and shift switches. The new circuits include a family of (4,2) and (7,3) parallel counters and an efficient 8 bit ripple-carry adder block. The circuits presented in this paper possess the following features: (1) compared with circuits employing binary logic schemes, a reduction of nearly 40-50% in worst-case power dissipation through the use of 4 bit state signals, where no more than half of the signal bits are subject to value-change at any logic stage; (2) high speed which is competitive with well-known circuits; (3) all critical paths contain only minimum-size buffers (inverters or NAND gates) whose nMOS and pMOS transistors can be minimum-sized with a negligible effect on circuit speeds; and (4) the height of any nMOS pass-transistor tree is no more than three. SPICE simulations have demonstrated the significant reduction in power dissipation and the competitive high speed of this approach, while the preliminary layouts of the circuits have illustrated the small VLSI area and the compactness of the design